URN	etd-0714104-111543
Author	Kai - Chieh
Author's Email Address	g9111760@yuntech.edu.tw
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Department	Mechanical Engineering
Year	2003
Semester	2
Degree	Master
Type of Document	Master's Thesis
Language	zh-TW.Big5 Chinese
Title	The Thermal and Mold Flow Analysis of Chip Scale Packages
Date of Defense	2004-06-30
Page Count	67
Keyword	mold flow FEM CFD thermal resistance resin bleeding wire sweep
Abstract	In this research, the C-MOLD and Moldflow software are used to simulate the wire sweep of both TSOP and £gBGA packages during encapsulation, the predicted results are compared with experimental measurements to verify the accuracy of simulations. The effect of the auxiliary hole on substrate and the offset between the chip and substrate center on the wire sweep and the differences of melt-front advancements between upper and lower mold cavities during encapsulation are discussed. In order to improve the resin bleeding, the mold flow performances of four substrate designs are compared. The effect of molding pressure and velocity in lower cavity on resin bleeding is discussed. The finite element solid model and CFD model of QFN package are built to simulate the thermal performance of the package under natural and forced convection conditions, the simulated results are compared with experimental measurements to verify the accuracy. Both the flat plate surface convection correlations and the surface convection correlations obtained from the CFD results are applied to finite element solid model to predict the thermal resistance of the package, and the results are compared with experimental measurements to discuss the accuracy. Also the thermal performance of £gBGA under natural and forced convection conditions is simulated by finite element solid model.
Advisory Committee	Yi-ming Jen - chair Yung-cheng Wang - co-chair Chia-lung Chang - advisor
Files	etd-0714104-111543.pdf indicate access worldwide
Date of Submission	2004-07-14